-- PWM Module
-- 8 bit wide control (256 speeds)


library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity PWM is
	port( clk : in std_logic;	-- 2.27 Mhz signal
			reset		: in std_logic;
			PWM : out std_logic;	-- pulse width modulated output
			speed : in std_logic_vector (7 downto 0)
			);
end PWM;


ARCHITECTURE design of PWM is

SIGNAL speedsig : std_logic_vector(7 downto 0);
SIGNAL count : std_logic_vector(7 downto 0);
SIGNAL PWM_sig : std_logic;

BEGIN

	PROCESS (clk, reset) 
	BEGIN

		if(reset = '0') then
			count <= "00000000"; --(OTHERS => '0');
			PWM_sig <= '0';
		elsif (clk'event and clk = '1') then
			count <= count + 1;
			
			if (count < speedsig) then
				PWM_sig <= '1';
			else 
				PWM_sig <= '0';
			end if;
		
		end if;

PWM <= PWM_sig;
speedsig <= speed;
END PROCESS;




END design;